Integrated memory devices typically include an array of memory storage locations, or cells, which are arranged in rows and columns. The memory cells are accessed for data storage or retrieval by providing an array address. The address is usually provided in two parts; a row address, and a column address. The memory device decodes the memory array addresses and accesses the appropriate memory cells.
A wide variety of access modes are known to those skilled in the art, including page mode. In a page mode operation a row of the memory array is accessed and remains accessed while different columns of the array are accessed by changing the column address. When all desired operations have been performed in a given page, the accessed row is closed. Prior to closing the row, however, all memory cell operations must be complete.
One memory cell operation which is particularly sensitive to the closing of an accessed row is the memory cell write operation. During a write operation, a memory cell is accessed and a write driver provides a data signal to be stored on the cell. In the worst case, data stored in a memory cell will have to be changed to an opposite data state during a write operation. Typical write operation implementation in a memory device deactivates the write driver early in the write operation, and allows a differential amplifier to drive digit lines to full power supply rails. This can result in a relatively lengthy delay in closing the accessed row. That is, an accessed row cannot be turned off until all memory cells fully store the desired data. The faster the completion of the write operation, therefore, the sooner the row can be closed.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device which can close an accessed memory array row in a shorter time period.